1. Field of the Invention
This invention relates to semiconductor memories and more particularly to split gate flash memories.
2. Description of Related Art
Referring to FIG. 1, a fragmentary sectional view of a conventional prior art split gate flash EPROM device 10 is shown which includes a P- substrate 11 with N+ S/D regions 15, 17 formed in substrate 11 on either side beneath a polysilicon 1 floating gate 14 formed above a thin tunnel oxide region 12 formed as a layer on substrate 11. Above the floating gate 14 is a thin ONO layer 16. At the ends of the tunnel oxide layer 12, floating gate 14 and ONO layer 16 are silicon dioxide spacer structures 18. Over the remainder of the substrate 11 gate oxide 13 and field oxide structures 9 are formed. Above the ONO layer 16, the spacer structures 18, the gate oxide 13 and field oxide structures 9 is formed a polysilicon 2 control gate layer 19. The edge of the floating gate 14 is adjacent to one S/D region 17 but is substantially spaced away from the other S/D region 15. The control gate 19 however, which overlies the floating gate 14 extends over the length of the portion of device 11 which is shown. The problem with the device of FIG. 1 is with charge retention due to the poor quality of the sidewall silicon dioxide.
U.S. Pat. No. 5,280,446 of Ma et al for "Flash EPROM Memory Circuit Having Source side Programming", U.S. Pat. No. 5,274,588 of Manzur et al for "Split-Gate for an EEPROM", and U.S. Pat. No. 5,194,925 of Ajika et al for "Electrically Programmable Non-Volatile Semiconductor Memory Device" show prior art split gate, flash EEPROM processes and structures.